RTL Verification Engineer

[학력 사항]

l  전자/반도체 관련 학과 학사 졸업 이상

 

[자격 요건 및 우대 사항]

경력 3년 ~ 12년

SoC 디지털 설계 혹은 검증 경험

다양한 IP RTL 설계 혹은 검증 경험

ARM CPU 사용 경험 / CPU Architecture 이해

AMBA BUS (APB, AHB, AXI, ACE) protocol 경험

Verilog HDL, SystemVerilog 사용 경험

Perl, Python 등의 script 사용 경험

C, C++ 사용 경험

UVM 검증 관련 경력자 우대 (UVM 검증 경험이 없어도 하만 내부 교육 과정으로 교육 가능합니다)

 

RTL Design Engineer

[담당업무]

디지털 논리회로 설계 및 기본 검증

IP의 설계사양 및 기본 아키텍쳐 개발

각 디자인 단계별 업무 : Lint, CDC, Synthesis, EQ, ECO(functional and Timing)

STA 수행 및 결과 분석

Physical Implementation 지원

 

[자격요건]

유관업무 경력 2년 이상

IC 설계 Flow 및 설계방법론에 대한 이해

Verilog/SystemVerilog를 활용한 RTL 논리회로 설계 지식

설계사양을 결정하고 이를 회로로 구현할 수 있는 능력

프로그래밍 스킬: C/C++, Perl/Shell script 능력

 

[우대사항]

ARM CPU와 AMBA bus에 대한 이해

저전력 설계 방법론(UPF)에 대한 이해

검증 방법론(UVM)에 대한 이해

외국어 우수자(영어)

 

 

 

RTL Frontend engineer (PI) Physical Implementation Engineer

 

PI(Frontend) Jobs: Design synthesis, layout information for place/cts/routing, cross check the QoR of place/CTS/routing, make timing constraints(sdc), timing eco (fix timing, fix drc - mttv, glitch noise, cpc, min_pulse), Equivalen check,Special clock net care,low power rule check,leakage optimization (w/ TECO),

 

PI(Frontend) tools: Design-compiler, DCG, PrimeTime, Formality, VCLP, GCA,Spyglass-LDRC

 

Responsibilities:

Solid experience in developing and owning full chip timing constraints for a complex, multi-voltage SoCs.

Solid experience in running physical-aware logic synthesis (DC-G or Genus) and achieving optimal synthesis QoR on high-performance and low power designs

Solid experience in developing power intent using UPF and running static low power verification tool like Synopsys VC-LP or similar tools

Solid experience in running gate level power estimation using Synopsys PrimeTime-PX

Developing the timing constraints and running the full-chip logic synthesis

Collaborating with DSP to accomplish the design closure for tape-out

Block-level PPA analysis for marketing and sales/BD support

Samsung design methodology support for ASIC customers

Good understanding of chip floor plan to get the best PPA during physical-aware synthesis    

 

RTL Backend Engineer (PD) Physical Design Engineer

Physical Verification of Low power and high frequency designs.
Block level/full chip Physical Design activities.
Self-motivated team player with strong problem-solving skills that can collaborate with various teams to achieve design goals.
Hands on Experience in areas of physical verification (DRC/LVS/ERC/ANT) using Calibre or equivalent.
Extensive experience and detailed knowledge in Cadence or Synopsys or Physical Design Tools
Hands on experience in some aspects of design flows such as floor planning, placement optimization, clock tree synthesis, routing, crosstalk avoidance and physical verification
Basic Knowledge on VLSI and basic Knowledge on Timing.
Hands on Experience in ICC, Innovus or equivalent.
Should have been familiarity with process nodes
Excellent written and verbal communication skills required
Proficiency in Tcl and Perl scripting is essential.
Experience on PrimeTime, StarRC-XT, Formality, Redhawk or equivalent will be preferred.
Desired skills- Provide technical guidance, Leadership quality