Qualifications

 More than 10 years experiences related with register-transfer-level (RTL) digital logic design,

functional verification methodology, static and formal verification, and FPGA & emulation a plus

 Bachelor’s degree in EE and related field is required

 Strong written and oral communications in the English language is a plus

 Build strong rapport and credibility with customer organizations while maintaining a company internal

network of contacts

 With strong communications and interpersonal skills

This experience should include some of the followings:

Job Experience Requirement

 Familiar with System Verilog, UVM is must

 Verification of Full SoC and IP level : Verilog RTL simulation is must, Validation of IP on FPGA

platform is a plus

 SOC work & verification with ARM Cores, protocols like AXI, ACE, APB ... a plus

 Familiar with mobile AP, memory spec. like DDR, LPDDR is a plus

 Familiar with FuSa chip design or requirements is a plus

Tool Experience

 Design and Simulation in RTL : Verilog-HDL, NC-Verilog, Xcelium, Questa, VCS

 RTL Debugger: DVE, Verdi, Indago & Visualizer

 Logic Synthesis : DC Complier is a plus

 Power verification : Power Pro, Spyglass, UPF flow verification is a plus

 FuSa: VC-Z01X, Xcelium-Safety is a plus